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1 ? 2004 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-5710/5 december 2004 3.3 volt time slot interchange digital switch 1,024 x 1,024 IDT72V70810 idt and the idt logo are trademarks of integrated device technology, inc. the st-bus ? is a trademark of mitel corp. functional block diagram rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 ode f0i v cc cs ds/ rd r/ w / wr a0-a7 gnd cco dta d8-d15/ ad0-ad7 tx0 tx1 tx2 tx3 tx4 tx5 tx6 tx7 as/ ale im clk fe/ hclk wfps reset 0 0 ri si d s d ri i tii i ci ti si d s features: ? 1,024 x 1,024 channel non-blocking switching at 8.192 mb/s ? per-channel variable or constant throughput delay ? automatic identification of st-bus ? /gci interfaces ? accepts 8 serial data streams of 8.192 mb/s ? automatic frame offset delay measurement ? per-stream frame delay offset programming ? per-channel high impedance output control ? per-channel processor mode ? control interface compatible to intel/motorola cpus ? connection memory block programming ? available in 64-pin thin plastic quad flatpack (tqfp) and 64-pin small thin quad flatpack (stqfp) ? 3.3v power supply ? operating temperature range -40 c to +85 c ? ? ? ? ? 3.3v i/o with 5v tolerant inputs description: the IDT72V70810 is a non-blocking digital switch that has a capacity of 1,024 x 1,024 channels at a serial bit rate of 8.192 mb/s. some of the main features are: programmable stream and channel control, processor mode, input offset delay and high-impedance output control. per-stream input delay control is provided for managing large multi-chip switches that transport both voice channel and concatenated data channels. in addition, input streams can be individually calibrated for input frame offset.
2 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 pin configuration tqfp 0.80mm pitch, 14mm x 14mm (pn64-1, order code: pf) stqfp 0.50 pitch, 10mm x 10mm (pp64-1, order code: tf) top view notes: 1. dnc - do not connect. 2. all i/o pins are 5v tolerant. pin 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vcc gnd tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 gnd cco dta d15 d14 ode d13 d12 d11 d10 d9 d8 gnd vcc ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gnd rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 f0i fe/hclk gnd clk vcc dnc dnc reset wfps a0 a1 a2 a3 a4 a5 a6 a7 ds/ rd cs as/ale im gnd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 5710 drw02 r/ w / rw 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
3 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 pin description symbol name i/o description gnd ground. ground rail. vcc vcc +3.3 volt power supply. tx0-7 tx output 0 to 7 o serial data output stream. these streams have a data rate of 8.192 mb/s. (three-state outputs) rx0-7 rx input 0 to 7 i serial data input stream. these streams have a data rate of 8.192 mb/s. f0i frame pulse i when the wfps pin is low, this input accepts and automatically identifies frame synchronization signals formatted according to st-bus ? and gci specifications. when the wfps pin is high, this pin accepts a negative frame pulse which conforms to wfps formats. fe/hclk frame evaluation/ i when the wfps pin is low, this pin is the frame measurement input. when the wfps pin is high, the hclk hclk clock (4.096 mhz clock) is required for frame alignment in the wide frame pulse (wfp) mode. clk clock i serial clock for shifting data in/out on the serial streams (rx/tx 0-7). this input accepts a 16.384 mhz clock. reset device reset i this input (active low) puts the IDT72V70810 in its reset state that clears the device internal counters, register s (schmitt trigger input) and brings tx0-7 and microport data outputs to a high-impedance state. the time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. in normal operation, the reset pin must be held low for a minimum of 100ns to reset the device. wfps wide frame i when 1, enables the wide frame pulse (wfp) frame alignment interface. when 0, the device operates in pulse select st-bus ? /gci mode. a0-7 address 0-7 i when non-multiplexed cpu bus operation is selected, these lines provide the a0-a7 address lines to the internal memories. ds/ rd data strobe/read i for motorola multiplexed bus operation, this input is ds. this active high ds input works in conjunction with cs to enable the read and write operations. for motorola non-multiplexed cpu bus operation, this input is ds. this active low input works in conjunction with cs to enable the read and write operations. for intel multiplexed bus operation, this input is rd . this active low input sets the data bus lines (ad0-7, d8-15) as outputs. r/ w / wr read/write / write i in the cases of motorola non-multiplexed and multiplexed bus operations, this input is r/ w . this input controls the direction of the data bus lines (ad0-7, d8-15) during a microprocessor access. for intel multiplexed bus operation, this input is wr . this active low input is used with rd to control the data bus (ad0-7) lines as inputs. cs chip select i active low input used by a microprocessor to activate the microprocessor port of IDT72V70810. as/ale address strobe or i this input is used if multiplexed bus operation is selected via the im input pin. for motorola non-mult iplexed latch enable bus operation, connect this pin to ground. im cpu interface mode i when im is high, the microprocessor port is in the multiplexed mode. when im is low, the microprocessor port is in non-multiplexed mode. ad0-7 address/data bus 0 to 7 i/o these pins are the eight least significant data bits of the microprocessor port. in multiplexed mode, these pins are also the input address bits of the microprocessor port. d8-15 data bus 8-15 i/o these pins are the eight most significant data bits of the microprocessor port. dta data transfer o this active low output signal indicates that a data bus transfer is complete. when the bus cycle ends, this pin acknowledgment drives high and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. a pull-up resistor is required to hold a high level when the pin is in high-impedance. cco control output o this is a 16.384 mb/s output containing 2.048 bits per frame respectively. the level of each bit is determine d by the cco bit in the connection memory. see external drive control section. ode output drive enable i this is the output enable control for the tx0 to tx7 serial outputs. when ode input is low and the osb bit of the ims register is low, tx0-7 are in a high-impedance state. if this input is high, the tx0-7 output drivers are enabled. however, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory.
4 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 functional description the IDT72V70810 is capable of switching up to 1,024 x 1,024, 64 kbit/s pcm or n x 64 kbit/s channel data. the device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. the serial input streams of the IDT72V70810 have a bit rate of 8.192 mb/s and are arranged in 125ms wide frames, which contain 128 channels. the data rates on input and output streams are identical. in processor mode, the microprocessor can access input and output time- slots on a per channel basis allowing for transfer of control and status information. the IDT72V70810 automatically identifies the polarity of the frame synchroni- zation input signal and configures the serial streams to either st-bus ? or gci formats. with the variety of different microprocessor interfaces, IDT72V70810 has provided an input mode pin (im) to help integrate the device into different microprocessor based environments: non-multiplexed or multiplexed. these interfaces provide compatibility with multiplexed and motorola non-multiplexed buses. the device can also resolve different control signals eliminating the use of glue logic necessary to convert the signals (r/ w / wr , ds/ rd , as/ale). the frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (fe). the input offset delay can be programmed for individual streams using internal frame input offset registers, see table 8. the internal loopback allows the tx output data to be looped around to the rx inputs for diagnostic purposes. a functional block diagram of the IDT72V70810 is shown in figure 1. data and connection memory the received serial data is converted to parallel format by internal serial- to-parallel converters and stored sequentially in the data memory. the 8 khz input frame pulse ( f0i ) is used to generate channel and frame boundaries of the input serial data. depending on the interface mode select (ims) register, the usable data memory may be as large as 1,024 bytes. data to be output on the serial streams (tx0-7) may come from either the data memory or connection memory. for data output from data memory (connection mode), addresses in the connection memory are used. for data to be output from connection memory, the connection memory control bits must set the particular tx output in processor mode. one time-slot before the data is to be output, data from either connection memory or data memory is read internally. this allows enough time for memory access and parallel-to-serial conversion. clock is required for data and connection memory access. connection and processor modes in the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. the connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. for details on the use of the source address data (cab and sab bits), see table 10. once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto a tx output stream. by having the each location in the connection memory specify an input channel, multiple outputs can specify the same input address. this can be a powerful tool used for broadcasting data. in processor mode, the microprocessor writes data to the connection memory. each location in the connection memory corresponds to a particular output stream and channel number and is transferred directly to the parallel-to- serial converter one time-slot before it is to be output. this data will be output on the tx streams in every frame until the data is changed by the microprocessor. as the IDT72V70810 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. specifically, the IDT72V70810 provides five per-channel control bits for the following functions: processor or connection mode, constant or variable delay, enables/three-state the tx output drivers and enables/disable the loopback function. in addition, one of these bits allows the user to control the cco output. if an output channel is set to a high-impedance state through the connection memory, the tx output will be in a high-impedance state for the duration of that channel. in addition to the per-channel control, all channels on the st-bus ? outputs can be placed in a high impedance state by either pulling the ode input pin low or programming the output stand-by (osb) bit in the interface mode selection register. this action overrides the per-channel programming in the connection memory bits. the connection memory data can be accessed via the microprocessor interface. the addressing of the devices internal registers, data and connection memories is performed through the address input pins and the memory select (ms) bit of the control register. for details on device addressing, see software control and control register bits description (table 3 and 5). serial data interface timing the master clock frequency must always be twice the data rate. for serial data rates of 8.192 mb/s, the master clock (clk) must be 16.384 mhz. the input and output stream data rates will always be identical. the IDT72V70810 provides two different interface timing modes st-bus ? / gci and wfp (wide frame pulse). if the wfps pin is high, the IDT72V70810 is in the wide frame pulse (wfp) frame alignment mode. in st-bus ? /gci mode, the input 8 khz frame pulse can be in either st-bus ? or gci format. the IDT72V70810 automatically detects the presence of an input frame pulse and identifies it as either st-bus ? or gci. in st-bus ? format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of clk, three quarters of the way into the bit cell, see figure 7. in gci format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of clk at three quarters of the way into the bit cell, see figure 8. wide frame pulse (wfp) frame alignment timing when the device is in wfp frame alignment mode, the clk input must be at 16.384 mhz, the fe/hclk input is 4.096 mhz and the 8 khz frame pulse is in st-bus ? format. the timing relationship between clk, hclk and the frame pulse is shown in figure 9. when wfps pin is high, the frame alignment evaluation feature is disabled. however, the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams. input frame offset selection input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. f0i ). although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. because data is often delayed, this feature is useful in compensating for the skew between clocks. each input stream can have its own delay offset value by programming the frame input offset registers (for). the maximum allowable skew is +4.5 master clock (clk) periods forward with resolution of ? clock period. the output frame
5 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 offset cannot be offset or adjusted. see figure 5, table 8 and 9 for delay offset programming. serial input frame alignment evaluation the IDT72V70810 provides the frame evaluation (fe) input to determine different data input delays with respect to the frame pulse f0i . a measurement cycle is started by setting the start frame evaluation (sfe) bit low for at least one frame. when the sfe bit in the ims register is changed from low to high, the evaluation starts. two frames later, the complete frame evaluation (cfe) bit of the frame alignment register (far) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the far register. the sfe bit must be set to zero before a new measurement cycle started. in st-bus ? mode, the falling edge of the frame measurement signal (fe) is evaluated against the falling edge of the st-bus ? frame pulse. in gci mode, the rising edge of fe is evaluated against the rising edge of the gci frame pulse. see table 7 & figure 4 for the description of the frame alignment register. this feature is not available when the wfp frame alignment mode is enabled (i.e., when the wfps pin is connected to vcc). memory block programming the IDT72V70810 provides users with the capability of initializing the entire connection memory block in two frames. to set bits 11 to 15 of every connection memory location, first program the desired pattern in bits 5 to 9 of the ims register. the block programming mode is enabled by setting the memory block program (mbp) bit of the control register high. when the block programming enable (bpe) bit of the ims register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. the other connection memory bits (bit 0 to bit 10) are loaded with zeros. when the memory block programming is complete, the device resets the bpe bit to zero. loopback control the loopback control (lpbk) bit of each connection memory location allows the tx output data to be looped backed internally to the rx input for diagnostic purposes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., data from tx n channel m routes to the rx n channel m internally); if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. delay through the IDT72V70810 the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabili- ties on the per-channel basis. for voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. in wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. the delay through the device varies according to the type of throughput delay selected in the v /c bit of the connection memory. variable delay mode ( v /c bit = 0) in this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. the minimum delay achievable in the IDT72V70810 is three time-slots. if the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). the same is true if input channel n is switched to output channel n+1 or n+2. if the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. table 1 shows the possible delays for the IDT72V70810 in the variable delay mode. constant delay mode ( v /c bit = 1) in this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. input channel data is written into the data memory buffers during frame n will be read out during frame n+2. in the IDT72V70810, the minimum throughput delay achievable in the constant delay mode will be one frame. see table 2 for possible delays in constant delay mode. microprocessor interface the IDT72V70810 provides a parallel microprocessor interface for multi- plexed or non-multiplexed bus structures. this interface is compatible with motorola non-multiplexed and multiplexed buses. if the im pin is low a motorola non-multiplexed bus should be connected to the device. if the im pin is high, the device monitors the as/ale and ds/ rd to determine what mode the IDT72V70810 should operate in. if ds/ rd is low at the rising edge of as/ale, then the mode 1 multiplexed timing is selected. if ds/ rd is high at the rising edge of as/ale, then the mode 2 multiplexed bus timing is selected. for multiplexed operation, the required signals are the 8-bit data and address (ad0-ad7), 8-bit data (d8-d15), address strobe/address latch enable (as/ ale), data strobe/read (ds/ rd ), read/write /write (r/ w / wr ), chip select ( cs ) and data transfer acknowledge ( dta ). see figure 12 and figure 13 for multiplexed parallel microport timing. for the motorola non-multiplexed bus, the required signals are the 16-bit data bus (ad0-ad7, d8-d15), 8-bit address bus (a0-a7) and 4 control lines ( cs , ds, r/ w and dta ). see figure 14 and 15 for motorola non-multiplexed microport timing. the IDT72V70810 microport provides access to the internal registers, connection and data memories. all locations provide read/write access except for the data memory and the frame alignment register which are read only. memory mapping the address bus on the microprocessor interface selects the internal registers and memories of the IDT72V70810. if the a7 address input is low, then a6 through a0 are used to address the interface mode selection (ims), control (cr), frame alignment (far) and frame input offset (for) registers (table 4). if the a7 is high, then a6 through a0 are used to select 128 locations corresponding to data rate of the st-bus ? . the address input lines and the stream address bits (sta) of the control register allow access to the entire data and connection memories. the control and ims registers together control all the major functions of the device, see figure 3. as explained in the serial data interface timing and switching configura- tions sections, after system power-up, the ims register should be programmed immediately to establish the desired switching configuration. the data in the control register consists of the memory block programming bit (mbp), the memory select bit (ms) and the stream address bits (sta). as explained in the memory block programming section, the mbp bit allows the entire connection memory block to be programmed. the memory select bit is used to designate the connection memory or the data memory. the stream address bits select internal memory subsections corresponding to input or output serial streams.
6 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 the data in the ims register consists of block programming bits (bpd0- bpd4), block programming enable bit (bpe), output stand by bit (osb) and start frame evaluation bit (sfe). the block programming and the block programming enable bits allows users to program the entire connection memory (see memory block programming section). if the ode pin is low, the osb bit enables (if high) or disables (if low) all st-bus ? output drivers. if the ode pin is high, the contents of the osb bit is ignored and all tx output drivers are enabled. connection memory control the cco pin is a 16.384 mb/s output, which carries 2,048 bits. the contents of the cco bit of each connection memory location are output on the cco pin once every frame. the contents of the cco bits of the connection memory are transmitted sequentially on to the cco pin (2 bit cells for each bit in connection memory) and are synchronous with the data rates on the other serial streams. the cco bit is output one channel before the corresponding channel on the serial streams. if the ode pin or the osb bit is high, the oe bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). see table 4 for detail. the processor channel (pc) bit of the connection memory selects between processor mode and connection mode. if high, the contents of the connection memory are output on the tx streams. if low, the stream address bit (sab) and the channel address bit (cab) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output from data memory. the v /c (variable/constant delay) bit in each connection memory location allows the per-channel selection between variable and constant throughput delay modes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., rx n channel m data comes from the tx n channel m). if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero. initialization of the IDT72V70810 after power up, the state of the connection memory is unknown. as such, the outputs should be put in high impedance by holding the ode low. while the ode is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the oe bit in connection memory. once the device is configured, the ode pin (or osb bit depending on initialization) can be switched.
7 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 connection memory channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 channel 0 channel 1 channel 2 channel 127 10000001 10000010 data memory 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 stream control register cr b 7 5710 drw03 10000000 the control register is only accessed when a7-a0 are all zeroed. when a7 =1, up to 128 bytes are randomly accessable via a0-a6 at any one instant. of which stream these bytes (channels) are accessed is determined by the state of cr b 2 -cr b 0. cr b 6cr b 5cr b 4cr b 3cr b 2cr b 1cr b 0 cr b 2cr b 1cr b 0 1 0 cr b 4 11111111 external address bits a7-a0 figure 3. addressing internal memories
8 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 table 4 output high impedance control table 3 internal register and address memory mapping table 2 constant throughput delay value table 1 variable throughput delay value note: 1. bit a7 must be high for access to data and connection memory positions. bit a7 must be low for access to registers. delay for variable throughput delay mode input rate (m ? output channel number) (n ? input channel number) m < n m = n, n+1, n+2 m > n+2 8.192 mb/s 128 ? (n-m) time-s lots m-n + 128 time-slots m-n time-slots delay for constant throughput delay mode input rate (m ? output channel number) (n ? input channel number) 8.192 mb/s 128 + (128 ? n) + m time-slots a7 (1) a6 a5 a4 a3 a2 a1 a0 location 00000000 control register, cr 00000001 interface mode selection register, ims 00000010 frame alignment register, far 00000011 frame input offset register 0, for0 00000100 frame input offset register 1, for1 10000000ch0 10000001ch1 100...... 10011110 ch30 10011111 ch31 10100000 ch32 10100001 ch33 101...... 10111110 ch62 10111111 ch63 11000000 ch64 11000001 ch65 110...... 11111110 ch126 11111111 ch127 oe bit in connection ode pin osb bit in ims tx output driver memory register status 0 don?t care don?t care per channel high-impedance 1 0 0 high-impedance 1 0 1 enable 1 1 1 enable 1 1 0 enable
9 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 table 5 control register (cr) bits table 6 interface mode selection (ims) register bits read/write address: 01 h , reset value: 0000 h . bit name description 15-10 unused must be zero for normal operation. 9-5 bpd4-0 these bits carry the value to be loaded into the connection memory block whenever the memory block (block programming data) programming feature is activated. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the contents of the bits bpd4-0 are loaded into bit 15 and 11 of the connection memory. bit 10 to bit 0 of the connection memory are set to 0. 4 bpe a zero to one transition of this bit enables the memory block programming function. the bpe and (begin block programming bpd4-0 bits in the ims register have to be defined in the same write operation. once the bpe bit is set enable) high, the device requires two frames to complete the block programming. after the programming function has finished, the bpe bit returns to zero to indicate the operation is completed. when the bpe = 1, the bpe or mbp can be set to 0 to abort to ensure proper operation. when bpe = 1, the other bit in the ims register must not be changed for two frames to ensure proper operation. 3 osb when ode = 0 and osb = 0, the output drivers of tx0 to tx7 are in high impedance mode. when (output stand by) ode= 0 and osb = 1, the output driver of tx0 to tx7 function normally. when ode = 1, tx0 to tx7 output drivers function normally. 2 sfe a zero to one transition in this bit starts the frame evaluation procedure. when the cfe bit in the far (start frame evaluation) register changes from zero to one, the evaluation procedure stops. to start another fame evaluation cycle, set this bit to zero for at least one frame. 1-0 unused for normal operation, bit 1 = 1 and bit 0 = 0. 1514131211109876543210 000000 bpd4 bpd3 bpd2 bpd1 bpd0 bpe osb sfe 1 0 read/write address: 00 h , reset value: 0000 h . 1514131211109876543210 0000000000mbpms0 sta2 sta1 sta0 bit name description 15-6 unused must be zero for normal operation. 5 mbp when 1, the connection memory block programming feature is ready for the programming of connection (memory block program) memory high bits, bit 11 to bit 15. when 0, this feature is disabled. 4 ms when 0, connection memory is selected for read or write operations. when 1, the data memory is selected (memory select) for read operations and connection memory is selected for write operations. (no microprocessor write operation is allowed for the data memory.) 3 unused must be zero for normal operation. 2-0 sta2-0 the binary value expressed by these bits refers to the input or output data stream, which corresponds (stream address bits) to the subsection of memory made accessible for subsequent operations. (sta2 = msb, sta0 = lsb)
10 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 0123 456 78 9101112131415 16 st-bus ? frame clk offset value fe input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gci frame clk offset value fe input (fd[10:0] = 06 h ) (fd11 = 0, sample at clk low phase) (fd[10:0] = 09 h ) (fd11 = 1, sample at clk high phase) 5710 drw04 table 7 frame alignment register (far) bits figure 4. example for frame alignment measurement bit name description 15-13 unused must be zero for normal operation. 12 cfe when cfe = 1, the frame evaluation is completed and bits fd10 to fd0 bits contains a valid frame alignment (complete frame evaluation) offset. this bit is reset to zero, when sfe bit in the ims register is changed from 1 to 0. 11 fd11 the falling edge of fe (or rising edge for gci mode) is sampled during the clk-high phase (fd11 = 1) (frame delay bit 11) or during the clk-low phase (fd11 = 0). this bit allows the measurement resolution to ? clk cycle. 10-0 fd10-0 the binary value expressed in these bits refers to the measured input offset value. these bits are rest to (frame delay bits) zero when the sfe bit of the ims register changes from 1 to 0. (fd10 ? msb, fd0 ? lsb) read/write address: 02 h , reset value: 0000 h . 1514131211109876543210 0 0 0 cfe fd11 fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0
11 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 table 8 frame input offset register (for) bits note: 1. n denotes an input stream number from 0 to 7. name (1) description ofn2, ofn1, ofn0 these three bits define how long the serial interface receiver takes to recognize and store bit 0 from the rx i nput pin: i.e., to (offset bits 2, 1 & 0) start a new frame. the input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the f0i input of the device. see figure 5. dlen (data latch edge) st-bus ? mode: dlen = 0, if clock rising edge is at the ? point of the bit cell. dlen = 1, if when clock falling edge is at the ? of the bit cell. gci mode: dlen = 0, if clock falling edge is at the ? point of the bit cell. dlen = 1, if when clock rising edge is at the ? of the bit cell. read/write address: 03 h for for0 register, 04 h for for1 register, reset value: 0000 h for all for registers. 1514131211109876543210 of32 of31 of30 dle3 of22 of21 of20 dle2 of12 of11 of10 dle1 of02 of01 of00 dle0 for0 register 1514131211109876543210 of72 of71 of70 dle7 of62 of61 of60 dle6 of52 of51 of50 dle5 of42 of41 of40 dle4 for1 register
12 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 st-bus ? f0i rx stream 5710 drw05 bit 7 bit 7 clk bit 7 bit 7 denotes the 3/4 point of the bit cell offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 offset = 1, dle = 1 gci f0i bit 0 bit 0 clk bit 0 bit 0 denotes the 3/4 point of the bit cell offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 offset = 1, dle = 1 rx stream rx stream rx stream rx stream rx stream rx stream rx stream table 9 offset bits (ofn2, ofn1, ofn0, dlen) & frame delay bits (fd11, fd2-0) figure 5. examples for input offset delay timing measurement result from corresponding input stream frame delay bits offset bits offset fd11 fd2 fd1 fd0 ofn2 ofn1 ofn0 dlen no clock period shift (default) 1000000 0 + 0.5 clock period shift 0000000 1 + 1.0 clock period shift 1001001 0 + 1.5 clock period shift 0001001 1 + 2.0 clock period shift 1010010 0 + 2.5 clock period shift 0010010 1 + 3.0 clock period shift 1011011 0 + 3.5 clock period shift 0011011 1 + 4.0 clock period shift 1100100 0 + 4.5 clock period shift 0100100 1
13 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 table 10 connection memory bits note: 1. if bit 13 (pc) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (sab 0, cab6 - cab0) are output on the output channel and stream associated with this location. bit name description 15 lpbk when 1, the rx n channel m data comes from the tx n channel m. for proper per channel loopback (per channel loopback) operations, set the delay offset register bits ofn[2:0] to zero for the streams which are in the loopback mode. 14 v /c this bit is used to select between the variable (low) and constant delay (high) mode on a (variable/constant per-channel basis. throughput delay) 13 pc when 1, the contents of the connection memory are output on the corresponding output channel and stream. (processor channel) only the lower byte (bit 7 ? bit 0) will be output to the tx output pins. when 0, the contents of the connec tion memory are the data memory address of the switched input channel and stream. 12 cco this bit is output on the cco pin one channel early. the cco bit for stream 0 is output first. (control channel output) 11 oe this bit enables the tx output drivers on a per-channel basis. when 1, the output driver functions (output enable) normally. when 0, the output driver is in a high-impedance state. 10 unused must be zero for normal operation. 9,8,7 (1) sab2-0 the binary value is the number of the data stream for the source of the connection. (source stream address bits) 6-0 (1) cab6-0 the binary value is the number of the channel for the source of the connection. (source channel address bits) 1514131211109876543210 lpbk v /c pc cco oe 0 sab2 sab1 sab0 cab6 cab5 cab4 cab3 cab2 cab1 cab0
14 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 recommended dc operating conditions dc electrical characteristics note: 1. voltages are with respect to ground unless other wise stated. note: 1. outputs unloaded. test point output pin c l gnd s 1 r l vcc gnd 5710 drw06 s 2 symbol parameter min. typ. max. units v cc positive supply 3.0 ? 3.6 v v ih input high voltage 2.0 ? vcc v v il input low voltage gnd ? 0.8 v t op operating temperature -40 ? +85 c commercial symbol characteristics min. typ. max. units i cc (1) supply current ? 30 45 m a i il input leakage (input pins) ?? 15 a i bl input leakage (i/o pins) ?? 50 a c i input pin capacitance ?? 10 pf i oz high-impedance leakage ?? 5 a v oh output high voltage 2.4 ?? v v ol output low voltage ?? 0.4 v c o output pin capacitance ?? 10 pf figure 6. output load s1 is open circuit except when testing output levels or high impedance states. s2 is switched to v cc or gnd when testing output levels or high impedance states. symbol parameter min. max. unit v cc supply voltage -0.3 5.0 v vi voltage on digital inputs gnd -0.3 5.5 v i o current at digital outputs 20 ma t s storage temperature -65 +125 c p d package power dissapation ? 1w note: 1. exceeding these values may cause permanent damage. functional operation under these conditions is not implied. absolute maximum ratings (1)
15 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 ac electrical characteristics - frame pulse and clk note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . symbol characteristics min. typ. max. units t fpw frame pulse width (st-bus ? , gci) ? bit rate = 8.192 mb/s 26 ? 80 ns t fps frame pulse setup time before clk falling (st-bus ? or gci) 5 ?? ns t fph frame pulse hold time from clk falling (st-bus ? or gci) 10 ?? ns t cp clk period ? bit rate = 8.192 mb/s 55 ? 70 ns t ch clk pulse width high ? bit rate = 8.192 mb/s 20 40 ns t cl clk pulse width low ? bit rate = 8.192 mb/s 20 ? 40 ns t r , t f clock rise/fall time ?? 10 ns t hfpw wide frame pulse width ? bit rate = 8.192 mb/s 195 ? 295 ns t hfps frame pulse setup time before hclk falling 5 ? 150 ns t hfph frame pulse hold time from hclk falling 10 ? 150 ns t hcp hclk (4.096 mhz) period ? bit rate = 8.192 mb/s 190 ? 300 ns t hch hclk (4.096 mhz) pulse width high ? bit rate = 8.192 mb/s 85 ? 150 ns t hcl hclk (4.096 mhz) pulse width low ? bit rate = 8.192 mb/s 85 ? 150 ns t hr , t hf hclk rise/fall time ?? 10 ns t dif delay between falling edge of hclk and falling edge of clk -10 ? 10 ns symbol characteristics min. typ. max. unit test conditions t sis rx setup time 0 ?? ns t sih rx hold time 10 ?? ns t sod tx delay ? active to active ?? 30 ns c l = 30pf ?? 40 ns c l = 200pf t dz tx delay ? active to high-z ?? 32 ns r l = 1k ? , c l = 200pf t zd tx delay ? high-z to active ?? 32 ns r l = 1k ? , c l = 200pf t ode output driver enable (ode) delay ?? 32 ns r l = 1k ? , c l = 200pf t xcd cco output delay ?? 30 ns c l = 30pf ?? 40 ns c l = 200pf ac electrical characteristics - serial streams (1)
16 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 bit 1, channel 0 bit 0, channel 0 bit 7, last ch (1) bit 2, channel 0 bit 1, channel 0 bit 0, channel 0 bit 7, last ch (1) bit 2, channel 0 t fpw t fph t ch t cl t f t r t fps t sod t sis t sih f0i clk tx rx t cp 5710 drw08 note : 1. last channel = ch 127. figure 8. gci timing when wfps pin = 0 t fpw t fph t ch t cl t f t r t fps t sod t sis t sih f0i clk tx rx t cp 5710 drw07 bit 6, channel 0 bit 7, channel 0 bit 0, last ch (1) bit 5, channel 0 bit 6, channel 0 bit 7, channel 0 bit 0, last ch (1) bit 5, channel 0 note: 1. last channel = ch 127. figure 7. st-bus ? timing when wfps pin = 0.
17 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 t xcd t zd clk (st-bus ? or wfps mode) clk (gci mode) cco 5710 drw10 tx tx valid data valid data t dz ode tx valid data 5710 drw11 t ode t ode figure 10. serial output and external control figure 11. output driver enable (ode) t hfph t dif f0i tx rx 5710 drw09 bit 1, ch 127 bit 0, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 1, ch 127 bit 0, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 t hfps t hfpw clk 16.384 mhz hclk 4.096 mhz t hch t hcp t cp t ch t cl t r t sod t f t sis t sih t hcl t hf t hr figure 9. wfp bus timing for high speed serial interface (8.192 mb/s), when wfps pin = 1 note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
18 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 t alw address data t ads t adh ale 5710 drw12 t rw t ww t csrw t alrd t csr t csw t dhw t dhr t akh t ddr t dsw t swd t alwr t akd ad0-ad7 d8-d15 cs rd wr dta figure 12. multiplexed bus timing (intel mode) ac electrical characteristics - multiplexed bus timing (intel) note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . symbol parameter min. typ. max. units test conditions t alw ale pulse width 20 ns t ads address setup from ale falling 3 ns t adh address hold from ale falling 3 ns t alrd rd active after ale falling 3 ns t ddr data setup from dta low on read 5 ns c l = 150pf t csrw cs hold after rd / wr 5ns t rw rd pulse width (fast read) 45 ns t csr cs setup from rd 0ns t dhr (1) data hold after rd 10 20 ns c l = 150pf, r l = 1k t ww wr pulse width (fast write) 45 ns t alwr wr delay after ale falling 3 ns t csw cs setup from wr 0ns t dsw data setup from wr (fast write) 20 ns t swd valid data delay on write (slow write) 122 ns t dhw data hold after wr inactive 5 ns t akd acknowledgment delay: reading/writing registers 43/43 ns c l = 150pf reading/writing memory 220/210 ns c l = 150pf t akh (1) acknowledgment hold time 22 ns c l = 150pf, r l = 1k
19 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 ds 5710 drw13 address t css t dsh t asw t csh t ddr t ads t adh ad0-ad7 d8-d15 wr cs dta data address data t rws t dws t swd t dhw t akd ad0-ad7 d8-d15 rd r/ w as t rwh t dhr t akh ac electrical characteristics - multiplexed bus timing (motorola) figure 13. multiplexed bus timing (motorola mode) symbol parameter min. typ. max. units test con ditions t asw ale pulse width 20 ns t ads address setup from as falling 3 ns t adh address hold from as falling 3 ns t ddr data setup from dta low on read 5 ns c l = 150pf t csh cs hold after ds falling 0 ns t css cs setup from ds rising 0 ns t dhw data hold after write 5 ns t dws data setup from ds ? write (fast write) 20 ns t swd valid data delay on write (slow write) 122 ns t rws r/ w setup from ds rising 60 ns t rwh r/ w hold from ds rising 5 ns t dhr (1) data hold after read 10 20 ns c l = 150pf, r l = 1k t dsh ds delay after as falling 10 ns t akd acknowledgment delay: reading/writing registers 43/43 ns c l = 150pf reading/writing memory 220/210 ns c l = 150pf t akh (1) acknowledgment hold time 22 ns c l = 150pf, r l = 1k note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
20 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 ds cs valid write address a0-a7 t css t csh r/ w t rws t rwh t ads t adh valid write data ad0-ad7/ d8-d15 t dsw t dhw dta t akd t akh t css t csh t rws t rwh valid read address t ads t adh valid read data t ddr t dhr t akd t akh 5710 drw14 figure 14. motorola non-multiplexed asyncronous bus timing ac electrical characteristics-motorola non-multiplexed bus mode symbol parameter min. typ. max. units test conditions t css cs setup from ds falling 0 ns t rws r/w setup from ds falling 10 ns t ads address setup from ds falling 2 ns t csh cs hold after ds rising 0 ns t rwh r/w hold after ds rising 2 ns t adh address hold after ds rising 2 ns t ddr data setup from dta low on read 2 ns c l = 150pf t dhr data hold on read 10 20 ns c l = 150pf, r l = 1k t dsw data setup on write (fast write) 5 ? ns t swd valid data delay on write (slow write) 122 ns t dhw data hold on write 5 ns t akd acknowledgment delay: reading/writing registers 43/43 ns c l = 150pf reading/writing memory 220/210 ns c l = 150pf t akh (1) acknowledgment hold time 22 ns c l = 150pf, r l = 1k note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
21 commercial temperature range IDT72V70810 3.3v time slot interchange digital switch 1,024 x 1,024 5710 drw15 ad0-ad7/ d8-d15 cs dta valid write address r/ w a0-a7 ds clk gci clk st-bus ? t dss t css t csh t rws t rwh valid read address t ads t adh valid read data t dhr t cka k t akh t ddr t dspw t dss t css t csh t rws t rwh t ads t adh valid write data t dhw t ckak t akh t swd figure 15. motorola non-multiplexed syncronous bus timing
22 corporate headquarter for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1552 santa clara, ca 95054 fax: 408-492-8649 email: telecomhelp@idt.com www.idt.com 5710 drw16 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 72v70810 1,024 x 1,024 ? 3.3v time slot interchange digital switch pf tf thin plastic quad flatpack (tqfp, pn64-1) small thin quad flat pack (stqfp, pp64-1) ordering information data sheet document history 5/02/2000 pg.1 1/04/2001 pgs. 4, 5, 10, 11, 14, 17, 19 and 20. 1/25/2001 pgs. 14 and 20. 08/06/2001 pg. 1 03/24/2003 pg. 1 12/07/2004 pgs. 4 and 7.

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